Press release

Imperas Delivers First RISC-V Simulator for New Vector and Bit Manipulation Specifications to Lead Customers

Sponsored by Businesswire

Software Ltd.
, the leader in virtual platforms and high-performance
software simulation, today announced the delivery of its updated
simulator for the RISC-V Vector and Bit Manipulation Extensions to lead
customers. In addition, the ratified RISC-V Specification is now
available in the free RISC-V Open Virtual Platform Simulator (riscvOVPsim™)
as a reference Instruction Set Simulator (ISS) for software
developers, implementers, and early adopters.

Imperas has supported many early stage implementations, customers and
RISC-V Foundation working group projects based on the previous draft
specifications of RISC-V and users can now use the same tools and
environment to seamlessly continue with the officially ratified
specifications. As a feature of Imperas’ simulation technology, all
previous specification versions remain available as configuration
options to allow software migration and implementation testing across
all releases of the RISC-V specifications. The RISC-V ISA (Instruction
Set Architecture) specification defines the boundary between software
and hardware and forms the basis for all developments with RISC-V.
Extensions allow a common set of features to be configured around the
base architecture and enable ecosystem development.

“Vector extension and Bit Manipulation will further expand the
applications of RISC-V based SoC and are in the Andes RISC-V CPU core
roadmap. We are glad to see Imperas take the lead to support them in
riscvOVPsim™ virtual platforms, which have migrated from use purely
within software teams to be used by SoC hardware design teams for system
level verification,” said Charlie Hong-Men Su, Andes Technology
. CTO and Executive Vice President. “Imperas and Andes have
developed a close working partnership founded around supporting our
mutual customers most complex design challenges with the latest RISC-V
specifications and extensions.”

“The Vectors and Bit Manipulation working groups of the RISC-V
Foundation are bringing members together to help define the next series
of extensions for RISC-V,” said Chris Jones, Codasip GmbH.
Vice President of Marketing. “Partnerships also help build ecosystems
and the latest models from Imperas will help the early adoption of these

“The vector extensions are a differentiating RISC-V feature, designed to
address the demanding applications such as machine learning and linear
algebra for next generation SoCs,” said Alexander Redkin, CEO of Syntacore.
“Early availability of high-quality simulators is pivotal for the
adoption of this extension.”

“RISC-V extensions for Vectors and Bit Manipulation are focused around
the combined hardware and software solutions for optimum design
efficiency,” said Dr. Luca Benini, Chair of digital circuits and systems
at ETH Zurich and University of Bologna, and one of the
originators of the PULP project, which develops and supports open-source
RISC-V cores with this extension: “Flexibility of software allows
designs to be tuned and adapted which can be best explored with the
reference models from Imperas for Vectors and Bit Manipulation.”

“The Bit Manipulation extensions give developers greater granularity on
data processing within the framework of the RISC-V architecture without
the need for a dedicated co-processor,” said Clifford Wolf, Symbiotic
CTO and Vice-Chair of the RISC-V Foundation Bit Manipulation
Extension working group
. “Software porting and development is
critical to the adoption of a new architecture and the first delivery of
models by Imperas now gives the industry the ideal reference starting
point for RISC-V Bit Manipulation extensions.”

“Compliance with the RISC-V ISA specifications is the essential
foundation for a complete ecosystem of compatible hardware and software
products,” said Allen Baum of Esperanto Technologies, Inc., who
chairs the RISC-V Foundation’s Technical Committee task
group for compliance
. “By supporting the latest
ratified specifications and the work of the Vector and Bit Manipulation
task groups, Imperas has been invaluable to the early development of
compliance tests for these new ISA extensions.”

“SoC verification represents one of the largest costs and schedule risk
factors for a complex design,” said Shubhodeep Roy Choudhury, Valtrix
Director & Co-founder. “Having used Imperas virtual platforms on
customer projects in conjunction with our STING test generator we see an
immediate advantage in easily modelling all the different customer
configurations using OVPsim models which include the RISC-V reference of
the ratified spec.”

“The ratification of the base RISC-V specification by the board and
members of the RISC-V Foundation marks an important milestone in the
history of RISC-V and will form the foundation of the ecosystem that is
developing around RISC-V,” said Simon Davidmann, president and CEO of Imperas
Software Ltd
. “Software developers, implementors and early adopters
of RISC-V Vectors and Bit Manipulation extensions can all test and
verify against a reference simulation based on Imperas leading
technology with confidence in the latest specifications.”

riscvOVPsim is free and available for download on GitHub as part
of the latest RISC-V compliance test suite and framework, available on
GitHub at
and as part of the Bit Manipulation reference at
riscvOVPsim includes a free to use license from Imperas, which supports
commercial as well as academic use. The open source model is licensed
under the Apache 2.0 license.


The free riscvOVPsim updates are available now on GitHub.

Imperas will demonstrate the new Vector and Bit Manipulation extensions
as well as other RISC-V models and virtual platforms, at the upcoming
RISC-V Workshop in Zurich Switzerland next week.

The riscvOVPsim solution is an entry ramp for development, as well as a
compliance testing tool. For developers of more advanced RISC-V designs,
who need multi-core support and advanced debug, verification and
analysis tools, Imperas also offers full-capability virtual platforms of
some leading RISC-V platforms including the multi-core SiFive U540 and
many others. Further details are available at

About Imperas

Imperas is revolutionizing the development of embedded software and
systems and is the leading provider of RISC-V processor models and
virtual prototype solutions. Imperas, along with Open Virtual Platforms
(OVP), promotes open source model availability for a spectrum of
processors, IP vendors, CPU architectures, system IP and reference
platform models of processors and systems ranging from simple single
core bare metal platforms to full heterogeneous multi-core systems
booting SMP Linux. All models are available from Imperas at
and the Open
Virtual Platforms (OVP)

For more information about Imperas, please see
Follow Imperas on LinkedIn,
@ImperasSoftware and YouTube.

About the RISC-V Foundation

For more information about RISC-V (pronounced “risk-five”), please see

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Software Limited or their respective holders.