Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Efinix successfully utilized the Cadence® digital full flow solution to complete the first wave of its Trion family of field programmable gate arrays (FPGAs), which are used in edge compute, AI/ML and vision processing applications for the mobile, industrial and surveillance markets. With the integrated Cadence RTL-to-signoff flow, Efinix engineers were able to achieve first-pass success across a spectrum of nodes down to 10nm. Based on Efinix’s successful collaboration with Cadence, the company plans to continue its use of the Cadence flow to grow its Trion product line.
For more information on the Cadence digital full flow solution, visit www.cadence.com/go/dffe.
The Efinix Trion product family offers its customers improved power, performance and area (PPA), and therefore they required advanced power and area optimization algorithms that support a variety of nodes. The Cadence digital full flow solution addressed Efinix’s requirements and provided the following benefits:
- Best-in-class design implementation and optimization: Cadence provides a unified physical optimization flow from RTL to GDSII with a common UI and database, allowing Efinix to have a seamless transition from physical synthesis to implementation
- Optimal signoff convergence: The Cadence digital full flow is the industry’s only digital flow solution with fully integrated place and route, timing signoff and IR drop/power signoff technologies, enabling Efinix to achieve faster design closure with fewer iterations to speed time to market
“We’re dedicated to continuous innovation, ensuring our Trion family of FPGAs for edge compute, AI/ML and vision processing segments meet the highest industry standards for excellence, “ said Tony Ngai, founder, CTO and SVP of engineering at Efinix. “Through our collaboration with Cadence and with the strength of their digital full flow solution, we were able to deliver the first wave of Trion family FPGAs in two years, from design start to mass production, successfully optimizing for the smallest silicon geometries to provide our customers with the best PPA.”
The Cadence digital full flow solution features the Genus™ Synthesis Solution, Innovus™ Implementation Solution, Tempus™ Timing Signoff Solution, Quantus™ Extraction Solution and Voltus™ IC Power Integrity Solution. The flow supports Cadence’s Intelligent System Design™ strategy, accelerating SoC design excellence and delivering better predictability.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health. For six years in a row, Fortune Magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
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