the leading provider of design constraints and verification solutions
that complement timing signoff for complex system-on-chip (SoC) designs,
has expanded its regional offices in India to support increasing
customer demand for the company’s flagship product TimevisionTM.
Pradeep CR has been appointed senior technical account manager at
Ausdia’s new location in Bangalore, India.
“We are very fortunate to have Pradeep, with his technical, regional and
industry knowledge, join our team and support the needs of our
customers,” said Sam Appleton, CEO, Ausdia. “The expansion of our team
reflects Ausdia’s commitment to our customers and our drive to address
the continuing challenges of SoC designs.”
Pradeep will support customers in the Asia Pac Rim region. As account
manager, he will support customers pre-and post sales. Prior to Ausdia,
Pradeep was a staff applications consultant for Synopsys Design
Methodology Solution (DMS) Products, chip-level static timing analysis
(STA) lead at Microchip (Formerly PMC Sierra), lead application engineer
at Extreme DA supporting GoldTime, field applications team supporting
Mentor Graphics AMS suite (CoreEL Technologies) and Field Applications
team supporting ASM assembly and fabrication product line.
Pradeep holds a bachelor’s degree in Electronics and Communications
Engineering from Visvesvaraya Technological University and a master’s
degree in VLSI System Design from Coventry University.
About Timevision Platform
Silicon design is becoming vastly more complicated and costly, and
harder to design and verify. This is due to raw design size, increasing
use of IP blocks, advanced technology nodes, number of clocks and
clocked domains, and complexity of constraints to close timing across
all combinations of corners and modes. There is a demand for a
comprehensive product to generate and validate design constraints that
correlate with static timing analysis engines to ensure design
correctness. By using multicore software architecture, patented analysis
algorithms, and innovative formal verification technology, the
Timevision platform was developed to handle large, complex SoC designs
(especially above 50M gates). Timevision integrates with all aspects of
the design flow and is used before synthesis, before DFT insertion,
before place and route, and when signoff timing is being run.
Ausdia will be showcasing the Timevision platform and the company’s
latest technology advances at the upcoming Design
Automation Conference (DAC), Booth 333, at the Las Vegas Convention
Center in Las Vegas, Nevada from Sunday, June 2 to Thursday, June 6.
Sign up today for a private
demo at DAC.
Ausdia Inc. is an experienced, trusted technology company solving
design’s toughest problems and transforming SoC design. The company is
focused on delivering proven design constraint development and
verification solutions that complement all implementation and timing
signoff flows. The company’s groundbreaking approach represents a
new way for SoC designers to enable massive productivity gains across
the design flow resulting in shrinking design time which ultimately
leads to a significant saving in design costs. Founded in 2006, Ausdia
has a combined experience of over 60 years in EDA development, chip
engineering and methodology. Ausdia is a privately-held company
headquartered in Sunnyvale, California. For more information visit www.ausdia.com