China’s YMTC Publishes Memory Patent Applications

Chinese memory chip maker YMTC has published nearly 20 new patent applications for processes to advance computing efficiency and optimise chip-making structures, according to local media reports, as the country pushes its semiconductor self-sufficiency drive.

It is known for the design and fabrication of 3D NAND flash memory, in which transistor dies are stacked vertically to increase storage density.

The company, which is under US trade sanctions, is nevertheless a leader in technologies such as Xtacking, a hybrid bonding technique designed to increase density while simplifying manufacturing processes.

Chip competition

The new patents were applied for between 2021 and 2023 and were published on 28 March, according to data from the China National Intellectual Property Administration cited by the South China Morning Post.

They include an improved stacking structure resistant to potential deformation, a method for shielding from electromagnetic interference and a method to boost storage density.

One of the patent applications involves modifying the way flash memory refreshes data, reducing the frequency of erasing the memory device to prolong its effective life.

Chinese companies are pushing to create independent intellectual property in the semiconductor industry amidst US trade sanctions designed to block China from developing advanced technology infrastructure.

Huawei Technologies separately in March disclosed a September 2023 patent application involving the use of ternary logic for the design of integrated circuits, while chip tool maker SiCarrier, which is backed by Huawei, unveiled new products for chip manufacturers at last month’s Semicon China exhibition.

Memory innovations

YMTC has developed a range of innovations with its Xtacking4.0 (Gen5) process in spite of US sanctions, Canadian research firm TechInsights said in a January report.

The process brings “notable advancements in process and design” aimed at enhancing storage density, speed and energy efficiency, TechInsights found.

The firm analysed the process used in YMTC’s highest-density 3D NAND flash memory chip, which TechInsights said it found in the commercial ZhiTai TiPro9000 storage device.

The chip uses a dual-deck structure, with 144 gates on the upper deck and 150 gates on the lower deck for a total of 294 gates and a hybrid-bonding technique joining the two together, TechInsights said.

The bonding process is now more refined than in previous iterations of Xtacking and is “the backbone of YMTC’s high-density, vertically connected 3D NAND chips”, the study said.