Engineers at Stanford University have outlined plans for a “skyscraper chip” based on carbon nanotube transistors (CNTs) that they say could boost performance and efficiency by a factor of one thousand over the conventional chips used today.
The design relies on stacking microprocessor components, rather than laying them out in a flat arrangement connected by wires, according to the team, led by Stanford’s Subhasish Mitra and H.-S. Philip Wong.
Stacked or three-dimensional chips have long been seen as a way of boosting chip performance, but until now little progress has been made toward building them. That’s in part because the fabrication of silicon-based components requires temperatures close to 1,800 degrees Fahrenheit, making it difficult to build one chip on top of another without damaging the first layer.
As a result, the current approach to building three-dimensional chips is to construct multiple layers separately, and then connect them using wires numbering in the thousands.
Carbon nanotubes require much lower temperatures, however, making it feasible to fabricate multiple layers simultaneously. Moreover, this approach to fabrication makes it possible to incorporate vertical interconnects numbering in the millions, shifting data at a higher rate. Since such interconnects move data over shorter distance than conventional wires, they also require less energy.
The approach, called Nano-Engineered Computing Systems Technology, or N3XT, is outlined in a special issue of the journal IEEE Computer.
“When you combine higher speed with lower energy use, N3XT systems outperform conventional approaches by a factor of a thousand,” Wong stated.
The N3XT architecture calls for layers of memory to be sandwiched between processor layers, so the team said it is experimenting with non-silicon memory technologies that can be built using the same lower-temperature fabrication process as the carbon nanotube transistors.
Those technologies include resistive random-access memory (RRAM) and a variety of nano-scale magnetic data storage materials, they said.
The N3XT design also incorporates thermal cooling layers to prevent the heat rising from stacked components from degrading performance, according to Stanford.
Mitra and Wong demonstrated a working four-layer prototype of a N3XT chip at the International Electron Devices Meeting in December 2014, with two layers of RRAM and two transistor layers.
Stanford computer scientist Chris Re, who contributed to the N3XT article, said the project could help open up access to critical data.
“There are huge volumes of data that sit within our reach and are relevant to some of society’s most pressing problems from health care to climate change, but we lack the computational horsepower to bring this data to light and use it,” Re stated.
The team admitted that adopting the N3XT approach would require “huge investments” from the industry, since it requires doing away with current silicon-based processes, but it argued the shift also promises “big payoffs”.
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