AMD is dedicating a new blog to its upcoming microprocessor architecture code-named Bulldozer
Advanced Micro Devices officials have launched a blog dedicated to the company’s upcoming “Bulldozer” processor architecture, which will be disclosed at a conference later in August.
Postings on The Bulldozer Blog, which launched on 2 Aug, will focus primarily on the commercial side of the business, though there will be some discussion of the consumer space, according to John Fruehe, director of product marketing for AMD server and workstation products, who wrote the first post.
“The server business tends to have much longer sales cycles and more architectural discussions, so you will see more focus from us in those areas,” Fruehe said.
Bulldozer is AMD’s first new microprocessor architecture in several years, and is aimed at the server and desktop PC spaces. AMD officials will give further details when they talk about the architecture at the Hot Chips conference on 24 Aug. at Stanford University in California.
Bulldozer And Bobcat
At the same time, they will give more details about “Bobcat,” a new core architecture for low-end, ultrathin notebooks and other smaller devices. Like Bulldozer, Bobcat will be coming out in 2011.
AMD officials aren’t giving out many details on Bulldozer, such as a precise launch date, pricing or benchmark results. However, with Bulldozer, AMD will be ramping up the number of cores on each chip. It will be included in new Opteron server processors, which will scale up to 16 cores. Chips with up to eight cores, targeted at PCs, will come out afterward.
The microprocessor architecture will offer not only more cores, but also greater performance than the current Opteron 60000 and 4000 series chips.
“There will be some new software instructions that will be supported, allowing for greater performance and flexibility, but it will be backward-compatible so you won’t need to change anything to start using the processor,” Fruehe said in his post.
Bulldozer also will offer a new floating point unit that can support up to 256-bit floating point execution, an important step for technical applications found in HPC (high-performance computing) environments.