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IBM Reveals World’s First 5nm Chip With 30bn Transistors

As News Editor of Silicon UK, Roland keeps a keen eye on the daily tech news coverage for the site, while also focusing on stories around cyber security, public sector IT, innovation, AI, and gadgets.

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Big Blue has moved away from FinFET to produce the tiny chip architecture

IBM has shown off the world’s first 5nm (nanometre) processor chip, ready to usher in more powerful yet more energy-efficient chips in the next three years. 

The tiny chip architecture is being championed by IBM as suitable for all manner of hardware applications, from powering servers supporting cloud services, to powering smart devices in the Internet of Things (IoT) and improving the battery life of mobile devices. 

“We are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors,” said Gary Patton, chief technology officer at GlobalFoundries, the company responsible for manufacturing the IBM chips. 

Silicon nanosheets 

Wafer of chips with 5nm silicon nanosheet transistorsWith 30 billion transistors packed onto a chip the size of a fingernail, the new 5nm chip is far more densely packed with transistors than the previous 7nm CPU IBM made a breakthrough with back in late 2015. 

To fit the amount of transistors on the chip without expanding its physical size saw IBM abandon the traditional FinFET (fin field effect) transistor design, which uses transistors with a 3D fins to fit multiple gate electrodes, the means by which it switches a transistor’s channel on or off, to a single transistor, and thus allow for more transistors to be fitted to a silicone chip. 

However, as the number of transistors on a chip increase, there are limitations to how far the FinFET fabrication technique can be taken. 

To fit 30 billion transistors onto a 5nm chip, IBM has moved away from the 3D FinFET technique and back into 2D chip building only with the expertise and techniques gleaned from using FinFET, such as ultraviolet lithography. 

Big Blue created the 5nm processor by using a technique called stacked silicon nanosheets, whereby transistors are layered on top of each other to pack the transistors more closely together, while the gate electrodes sit in between the layers of horizontal silicone rather than on a 3D fin, essentially making the gate as wide as the transistor and allowing for more reliable and higher performance over FinFET according to IBM. 

With the switch now in layers rather than on fins it is possible to better tune the circuits in CPUs to maximise their performance. 

Unfortunately, 5nm chips will not be arriving for at least another year, as the chip design is more a research and showcase by IBM that it is possible to extract performance out of such a tiny chip . 

The technology world has still got to wait until at least 2018 at the earliest to get its hands on the 7nm process IBM created, so we can forecast that the 5nm architecture will not be released into the wilds of the tech industry before 2020. 

In the meantime, the chips running the densest numbers of transistors for their size are the 10nm chips from the likes of  Qualcomm with its Snapdragon 835, a mobile chipset that has been tweaked to support Windows 10 despite lacking the x86 architecture normally needed to run Microsoft’s operating system. 

With IBM also building quantum processors, it is no surprise to see Big Blue come out with chips that push the boundaries of Moore’s Law, which is looking to have slowed down in recent years. 

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